There has been a continuous move in the computer industry generally to reduce the costs of computer systems, including both high- and low-end systems. Along with this overall cost reduction, there has been a continuous challenge in the disc drive industry to reduce the cost per megabyte of data stored, as well as increasing disc drive performance (e.g. faster access time) and increased storage capacity. This need for increased performance and higher capacity have been motivated by at least two factors. First, the increasing proliferation of digital data, including textual data, graphical data, and multimedia and audio-visual data, as well as the proliferation of information on the Internet and Worldwide Web which have resulted in a need for substantially more storage on each machine. Furthermore as operating systems and software application programs become more sophisticated and provide more features, the storage requirements for these programs and the data that they operate on have increased dramatically. Second, there has been a requirement for increased performance of disc drive systems generally. For example, computer systems that support multi-media functionality require reduced or fast access times to stored data so that graphical or imagery data can be accessed and presented to the user in real time. Program code must also be readily available so the execution is not inhibited by slow disc access. Where analog and/or digital data streams are to be captured from an external source, such as video cameras and the like, fast real time performance is mandatory, so that data streams are not corrupted or data is lost during real-time collection.
As consumer and professional demand for these low cost, high capacity, high performance non-volatile storage system grows, the pressure to create new and innovated solutions has been tremendous. One area where performance advantages may be realized along with a reduction in cost is in the area of the disc drive electronics. The advancement of semiconductor technologies has generally enabled disc drive designers and manufacturers to enhance the capabilities and performance of the integrated circuits while driving production and ultimately sales costs down. But these advancements have been limited.
A typical conventional constellation of electronics in a state of the art disc drive today has heretofore included four application specific integrated circuit (ASIC) devices. They are (1) read/write channel electronics, (2) servo power electronics, (3) processor or central processing unit (CPU), and (4) interface/disc/servo controller electronics. An example of the current generation of disc drive electronics and the associated disc drive hardware and interface is illustrated in FIG. 1 which is a diagram that shows the functional disc drive components, electronics, and their connectivity.
With further reference to FIG. 1, the disc drive electronics 30 includes a host interface 39 for connecting the disc drive to the host computer 80 (of any conventional design), and a Head Disc Assembly Interface (HDAI) 38 for connecting the disc drive electronics 30 to the head disk assembly (HDA) 82 itself including to read/write transducer head(s) 40 via wires 46, spindle motor 41, actuator motor 47, actuator arm 42, and other conventional disc drive components which are well known in the art and not discussed further. Many different types of disc drive are known in the art and the particular features of the disc drive illustrated in the figures is not meant to limit the applicability of the invention in any way. For simplicity and so as not to obscure the inventive feature, conventional components which would readily be understood to be present by those having ordinary skill in the art are not shown or described.
In this conventional implementation interface/disc/servo controller 31 provides an interface between the host computer and the disc drive with host interface 39. The interface is directly connected to buffer memory 32 which may store program code and/or data. Interface/disc/servo controller 31 is also connected by an 8- or 16-bit data bus 44 to CPU 34, code memory 35, and servo power electronics 36. Servo power electronics 36 is typically connected to the Hard Disc Assemblies (HDA) 82 via a direct connector connection 83 (typically implemented as a through hole or pressure connector) and through a plurality of FET switches 37 which control the spin motor. The HDA Interface (HDAI) 38 provides electrical connection between the Printed Circuit Board Assembly (PCBA) 84 including the internal disc drive electronics and HDA 82 including the disc drive internal mechanical and electromechanical components. Read/write channel electronics 33 includes Read Logic 33a, Write Logic 33b, and Servo Logic 33c, and is typically provided with a direct connection to interface/disc/servo controller 31 for transmitting user data to and from these devices via a 2-, 4-, or 8-bit NRZ data bus 42. A serial bus 43, is typically used to send configuration commands from the CPU 34 to the Read/Write Channel Electronics 33.
This conventional configuration provides for a CPU 34 that may operate by accessing program code from both the code memory 35 and from the buffer memory 32. However, CPU 34 and disc drive performance when running code from buffer memory 32 is degraded. The primary contributor to this performance degradation is the timing overhead associated with the multi-chip communication paths when the disc drive electronics 30 are implemented with chips. These multi-chip communication paths include: (1) the path from buffer memory 32 (chip A) to the CPU (Chip B) which passes through interface 31 (Chip C); and (2) the path from CPU 34 (Chip B) to code memory 35 (Chip D) over the bus 44.
FIG. 2 is a simplified diagrammatic illustration of a conventional three chip implementation for RAM core implementing buffer memory 32, Disc Controller Core 31, and CPU Core 34 configuration. In this configuration, the CPU 34 electrical connectivity path to and from the buffer memory 32 in the RAM core includes the following elements: (1) CPU logic 34, (2) first I/O pad 86, (3) first Bond wire 87, (4) first Lead Frame 88, (5) first PCBA trace 89, (6) second Lead Frame 90, (7) second Bond Wire 91, (8) second I/O pad 92, (9) Disc Controller logic 31, (10) third I/O pad 93, (11) third Bond Wire 94, (12) third Lead Frame 95, (13) third PCBA trace 96, (14) fourth Lead Frame 97, (15) fourth Bond Wire 98, (16) fourth I/O pad 99, and (17) RAM memory 32. In the circuit of FIG. 2, the non-logic elements may typically represent more than 60% of the time required to read or write the memory.
A major component of the electronic timing delays are the multi-chip communication paths caused by the large physical size of the integrated circuit (IC), I/O Driver (PADs) which are required to drive the large capacitive load presented by the PCBA traces, device package leads, and PAD inputs/outputs of connected integrated circuits.
In these conventional configurations the processor or CPU requests access to buffer memory 32 indirectly through controller logic within the interface/disc/servo controller 31. (Direct communication or access between CPU 34 and buffer memory 32 is not supported in the conventional implementation.) This indirect access from the processor to the buffer memory through the controller logic 31 causes additional timing overhead since access to the buffer memory by the CPU can only occur over bus 44 through interface/disc/servo controller 31 and then to the buffer memory over RAM bus 49. The pad/pin delays, including I/O leakage, trace capacitance, and I/O capacitance, associated with multiple ASIC chips in the conventional implementation may also typically introduce additional communication timing overhead which degrades disc drive performance. These factors generally decrease performance and have a particularly negative impact on disc drive performance when running code from the buffer memory 32.
The conventional implementation which uses multiple chips (typically four ASIC chips) degrades performance, and the timing overhead associated with accesses to individual registers in the disc controller 31 and in buffer memory 32 further degrades performance as compared to a theoretical integrated device.
Therefore, it will be seen that there is a need for a disc drive controller and processor configuration which overcomes these limitations and provides communication pathways and structure with direct access to both registers in the Disc Controller 31 and in buffer memory 32, and furthermore a configuration which reduces the total chip count to minimize manufacturing cost and enhance reliability. These and other features and advantages are provided by the inventive structure and method described in detail hereinafter.